1. Field of the Invention
The present invention generally relates to a semiconductor integrated circuit operable as a phase-locked loop, and more particularly, to a semiconductor integrated circuit operable as a phase-locked loop which generates an extremely stable high-frequency oscillation signal.
The present invention is also directed to a semiconductor integrated circuit operable as a clock recovery circuit using a phase-locked loop.
2. Description of the Related Art
FIG. 1 shows a first configuration example of a prior art semiconductor integrated circuit using a phase-locked loop (PLL). A semiconductor integrated circuit 9A is constructed with an oscillator 3, a divider 4, a phase comparator (also referred to as a phase detector) 1, and a loop filter 2.
The oscillator 3 generates an oscillation output signal 3a whose frequency is n times a frequency of input data 1b and is controlled by an oscillation-frequency control signal 2a. In the divider 4, the frequency of the oscillation output signal 3a is divided by n (n is a division ratio, n=1, 2, 3 . . . ) to produce a divided signal 4a.
The phase comparator 1 compares the frequency of the divided signal 4a with the frequency of the input data 1b, and outputs a phase comparison signal 1a according to a difference of their frequencies. The loop filter 2 integrates the phase comparison signal 1a and converts it into the oscillation-frequency control signal 2a.
In this way, in the PLL circuit used in the semiconductor integrated circuit 9A, a feedback loop, in which the oscillation output signal 3a is fed back to the phase comparator 1 through the divider 4, is formed.
FIG. 2 shows a second configuration example of the prior art semiconductor integrated circuit using the PLL. FIG. 3 shows a timing chart of the second configuration example of the prior art semiconductor integrated circuit shown in FIG. 2. In a semiconductor integrated circuit 9C shown in FIG. 2, in addition to the PLL circuit of the semiconductor integrated circuit 9A, a retiming block 9B is provided, and thus, the semiconductor integrated circuit 9C may be operative as a timing (clock) recovery circuit. The retiming block 9B generates retiming data 6a from the input data 1b based on the oscillation output signal 3a (recovered clock) of the oscillator 3.
The retiming block 9B is constructed with a pulse generating circuit 5, a retiming circuit 6, and a delay circuit 7. As shown in FIG. 3, the pulse generating circuit 5 detects a transition timing (an edge) of the input data 1b, and generates a detected pulse signal 5a so as to be triggered by the transition timing. The delay circuit 7 delays the oscillation output signal 3a of the oscillator 3 and transits delayed data 7a to the retiming circuit 6. The retiming circuit 6 operates a retiming operation, and generates the retiming data 6a from the input data 1b based on the delayed data 7a.
The PLL circuit is provided as a feedback loop between the pulse generating circuit 5 and the delay circuit 7, and is operative so that the pulse edge of the oscillation output signal 3a is positioned in a center of one pulse of the detected pulse signal 5a.
However, there are the following problems in the above-discussed prior art semiconductor integrated circuits 9A, 9C.
In the semiconductor integrated circuit 9A shown in FIG. 1, when the high-frequency oscillation output signal 3a is generated by multiplying the low-frequency input data 1b, and when the multiplication ratio (equal to the division ratio n) is large, the PLL operation becomes unstable. As a result, there is a problem in that it is difficult to generate the oscillation output signal 3a having an extremely stable frequency for a large division ratio.
For example, when the frequencies of the oscillation output signal 3a and the input data 1b are respectively 100 MHz and 1 MHz (namely, the division ratio is 100), only one pulse of the input data 1b is supplied to the phase comparator 1 during the time the oscillator 3 operates so as to generate 100 pulses.
Therefore, a sufficient number of phase comparing operations between the input data 1b and the oscillation output signal 3a are not carried out, and, thus, the PLL operation becomes unstable. As a result, a frequency shift may occur between the frequency of the oscillation output signal 3a and a desired frequency obtained by multiplying the frequency of the input data 1b by the division ratio n. Thus, a high stability of the oscillation output signal 3a may not be obtained.
On the other hand, in the semiconductor integrated circuit 9C shown in FIG. 2, the input data 1b is not a regular alternating signal, and changes substantially at random such as a demodulated signal. Therefore, a degree of the oscillator frequency control signal transmitted to the oscillator 3 decreases as compared to the conventional PLL circuit (successive data is provided to the phase comparator 1 as the reference signal). Accordingly, there is a problem in that an operation of the PLL circuit in the timing recovery circuit becomes unstable, and an error may occur in the retiming data 6a.
Further, in the retiming block 9B, the delay circuit 7 delays the oscillation output signal 3a so that the pulse edge of the oscillation output signal 3a is positioned in the center of one pulse of the detected pulse signal 5a. However, the delay time by the delay circuit 7 may easily be influenced from an outside temperature, fluctuation of an operation power source, manufacture dispersion, etc. As a result, there is a problem in that an error may occur in the retiming data 6a.